COMMODORE 128 INPUT/OUTPUT ASSIGNMENTS Differences Between C64 and C128 D500-D50B MMU D600-D601 VDC FF00-FF05 Preconfiguration Registers HEX DECIMAL BITS DESCRIPTION 8502 I/O Registers C128 mode: 0000 x 0 1 0 1 1 1 1 0001 x Caps Motor Sense Write HiRes LoRes Color C64 mode: 0000 0 7-0 MOS 8502 Data Direction Register (xx101111) Bit= 1: Output, Bit=0: Input, x=Don't Care 0001 1 MOS 8502 Micro-Processor On-Chip I/O Port 0 /LORAM Signal (0=Switch BASIC ROM Out) 1 /HIRAM Signal (0=Switch Kernal ROM Out) 2 /CHAREN Signal (O=Swith Char. ROM In) 3 Cassette Data Output Line 4 Cassette Switch Sense: 1 = Switch Closed 5 Cassette Motor Control O = ON, 1 = OFF 6-7 Undefined D000-D02E 53248-54271 MOS 6566 VIDEO INTERFACE CONTROLLER (VIC) D000 53248 Sprite O X Pos D001 53249 Sprite O Y Pos D002 53250 Sprite 1 X Pos D003 53251 Sprite 1 Y Pos D004 53252 Sprite 2 X Pos D005 53253 Sprite 2 Y Pos D006 53254 Sprite 3 X Pos D007 53255 Sprite 3 Y Pos D008 53256 Sprite 4 X Pos D009 53257 Sprite 4 Y Pos D00A 53258 Sprite 5 X Pos D00B 53259 Sprite 5 Y Pos D00C 53260 Sprite 6 X Pos D00D 53261 Sprite 6 Y Pos D00E 53262 Sprite 7 X Pos D00F 53263 Sprite 7 Y Pos D010 53264 Sprites 0-7 X Pos (msb of X coord.) D011 53265 VIC Control Register 7 Raster Compare: (Bit 8) See 53266 6 Extended Color Text Mode 1 = Enable 5 Bit Map Mode. 1 = Enable 4 Blank Screen to Border Color: O = Blank 3 Select 24/25 Row Text Display: 1 = 25 Rows 2-0 Smooth Scroll to Y Dot-Position (0-7) D012 53266 Read Raster / Write Raster Value for Compare IRQ D013 53267 Light-Pen Latch X Pos D014 53268 Light-Pen Latch Y Pos D015 53269 Sprite display Enable: 1 = Enable D016 53270 VIC Control Register 7-6 Unused 5 ALWAYS SET THIS BIT TO 0 ! 4 Multi-Color Mode: 1 = Enable (Text or Bit-Map) 3 Select 38/40 Column Text Display: 1 = 40 Cols 2-0 Smooth Scroll to X Pos D017 53271 Sprites O-7 Expand 2x Vertical (Y) D018 53272 VIC Memory Control Register 7-4 Video Matrix Base Address (inside VIC) 3-1 Character Dot-Data Base Address (inside VIC) 0 Select upper/lower Character Set D019 53273 VIC Interrupt Flag Register (Bit = 1: IRQ Occurred) 7 Set on Any Enabled VIC IRQ Condition 3 Light-Pen Triggered IRQ Flag 2 Sprite to Sprite Collision IRQ Flag 1 Sprite to Background Collision IRQ Flag 0 Raster Compare IRQ Flag D01A 53274 IRQ Mask Register: 1 = Interrupt Enabled D01B 53275 Sprite to Background Display Priority: 1 = Sprite D01C 53276 Sprites O-7 Multi-Color Mode Select: 1 = M.C.M. D01D 53277 Sprites 0-7 Expand 2x Horizontal (X) D01E 53278 Sprite to Sprite Collision Detect D01F 53279 Sprite to Background Collision Detect D020 53280 Border Color D021 53281 Background Color O D022 53282 Background Color 1 D023 53283 Background Color 2 D024 53284 Background Color 3 D025 53285 Sprite Multi-Color Register 0 D026 53286 Sprite Multi-Color Register 1 D027 53287 Sprite O Color D028 53288 Sprite 1 Color D029 53289 Sprite 2 Color D02A 53290 Sprite 3 Color D02B 53291 Sprite 4 Color D02C 53292 Sprite 5 Color D02D 53293 Sprite 6 Color D02E 53294 Sprite 7 Color D02F 53295 7-3 Unused 2-0 Additional Keyboard Columns D030 53296 7-2 Unused 1 Test 0 2 MHz Mode D400-D4FF 54272-52527 MOS 6581 SOUND INTERFACE DEVICE (SID) D400 54272 Voice 1: Frequency Control - Low-Byte D401 54273 Voice 1: Frequency Control - High-Byte D402 54274 Voice 1: Pulse Waveform Width - Low-Byte D403 54275 7-4 Unused 3-0 Voice 1: Pulse Waveform Width - High-Nybble D404 54276 Voice 1: Control Register 7 Select Random Noise Waveform, 1 = On 6 Select Pulse Waveform, 1 = On 5 Select Sawtooth Waveform, 1 = On 4 Select Triangle Waveform, 1 = On 3 Test Bit: 1 = Disable Oscillator 1 2 Ring Modulate Osc. 1 with Osc. 3 Output, 1 = On 1 Synchronize Osc. 1 with Osc. 3 Frequency, 1 = On 0 Gate Bit: 1 = Start Att/Dec/Sus, 0 = Start Release D405 54277 Envelope Generator 1: Attack / Decay Cycle Control 7-4 Select Attack Cycle Duration: O-15 3-0 Select Decay Cycle Duration: 0-15 D406 54278 Envelope Generator 1: Sustain / Release Cycle Control 7-4 Select Sustain Cycle Duration: O-15 3-0 Select Release Cycle Duration: O-15 D407 54279 Voice 2: Frequency Control - Low-Byte D408 54280 Voice 2: Frequency Control - High-Byte D409 54281 Voice 2: Pulse Waveform Width - Low-Byte D40A 54282 7-4 Unused 3-0 Voice 2: Pulse Waveform Width - High-Nybble D40B 54283 Voice 2: Control Register 7 Select Random Noise Waveform, 1 = On 6 Select Pulse Waveform, 1 = On 5 Select Sawtooth Waveform, 1 = On 4 Select Triangle Waveform, 1 = On 3 Test Bit: 1 = Disable Oscillator 1 2 Ring Modulate Osc. 2 with Osc. 1 Output, 1 = On 1 Synchronize Osc. 2 with Osc. 1 Frequency, 1 = On 0 Gate Bit: 1 = Start Att/Dec/Sus, 0 = Start Release D40C 54284 Envelope Generator 2: Attack / Decay Cycle Control 7-4 Select Attack Cycle Duration: O-15 3-0 Select Decay Cycle Duration: 0-15 D40D 54285 Envelope Generator 2: Sustain / Release Cycle Control 7-4 Select Sustain Cycle Duration: O-15 3-0 Select Release Cycle Duration: O-15 D40E 54286 Voice 3: Frequency Control - Low-Byte D40F 54287 Voice 3: Frequency Control - High-Byte D410 54288 Voice 3: Pulse Waveform Width - Low-Byte D411 54289 7-4 Unused 3-0 Voice 3: Pulse Waveform Width - High-Nybble D412 54290 Voice 3: Control Register 7 Select Random Noise Waveform, 1 = On 6 Select Pulse Waveform, 1 = On 5 Select Sawtooth Waveform, 1 = On 4 Select Triangle Waveform, 1 = On 3 Test Bit: 1 = Disable Oscillator 1 2 Ring Modulate Osc. 3 with Osc. 2 Output, 1 = On 1 Synchronize Osc. 3 with Osc. 2 Frequency, 1 = On 0 Gate Bit: 1 = Start Att/Dec/Sus, 0 = Start Release D413 54291 Envelope Generator 3: Attac/Decay Cycle Control 7-4 Select Attack Cycle Duration: O-15 3-0 Select Decay Cycle Duration: 0-15 D414 54285 Envelope Generator 3: Sustain / Release Cycle Control 7-4 Select Sustain Cycle Duration: O-15 3-0 Select Release Cycle Duration: O-15 D415 54293 Filter Cutoff Frequency: Low-Nybble (Bits 2-O) D416 54294 Filter Cutoff Frequency: High-Byte D417 54295 Filter Resonance Control / Voice Input Control 7-4 Select Filter Resonance: 0-15 3 Filter External Input: 1 = Yes, 0 = No 2 Filter Voice 3 Output: 1 = Yes, 0 = No Filter Voice 2 Output: 1 = Yes, 0 = No 0 Filter Voice 1 Output: 1 = Yes, 0 = No D418 54296 Select Filter Mode and Volume 7 Cut-Off Voice 3 Output: 1 = Off, O = On 6 Select Filter High-Pass Mode: 1 = On 5 Select Filter Band-Pass Mode: 1 = On 4 Select Filter Low-Pass Mode: 1 = On 3-0 Select Output Volume: 0-15 D419 54297 Analog/Digital Converter: Game Paddle 1 (O-255) D41A 54298 Analog/Digital Converter Game Paddle 2 (O-255) D41B 54299 Oscillator 3 Random Number Generator D41C 54230 Envelope Generator 3 Output MMU $D500 and $FF00 C128 MMU 8722 D500 Configuration Register (CR) 7-6 RAM-select 0-3 5-4 High RAM/ROM 00 System ROM (Kernel, Edit) 01 Internal Function ROM 10 External Function ROM 11 RAM NOTE: I/O overrides all of these. 3-2 Mid RAM/ROM 00 System ROM (Basic HI) 01 Internal Function ROM 10 External Function ROM 11 RAM 1 Lo RAM 0 System ROM (Basic LO) 1 RAM 0 C.GEN 0 I/O 1 ROM/RAM D501 Preconfiguration Registers D502 D503 D504 D505 7 40/80 read only 6 C64 Mode (0 = C128) 5 EXROM: C64 (1 = C128) read only 4 GAME: C64 (1 = C128) read only 3 FSDIR: Fast Disk 2-1 - 0 Z80/8502 D506 RAM Configuration Register (RCR) 7-6 Video-Bank 5-4 - 3 Shared RAM Hi 2 Shared RAM Lo 1-0 Shared RAM Size: 00 = 1K, 01 = 4K, 10 = 8K, 11 = 16K D507 Zero Page Pointer Lo 7-0 A15-A8 D508 Zero Page Pointer Hi 7-4 - 3-2 A19-A18 (Used in 1MB System) 1-0 A17-A16 (256K System) D509 Stack Page Pointer Lo D50A Stack Page Pointer Hi D50B MMU Version Register 7-4 Bank Version (2 = 128K) 3-0 MMU Version Default Memory Configurations Bank FF00 Free RAM Space RAM I/O ROM 0 3f 0000-ffff 0 1 7f 0000-ffff 1 2 bf 0000-ffff 2 3 ff 0000-ffff 3 4 16 0000-7fff 0 I/O Int 5 56 0000-7fff 1 I/O Int 6 96 0000-7fff 2 I/O Int 7 d6 0000-7fff 3 I/O Int 8 2a 0000-7fff 0 I/O Ext 9 6a 0000-7fff 1 I/O Ext 10 aa 0000-7fff 2 I/O Ext 11 ea 0000-7fff 3 I/O Ext 12 06 0000-7fff 0 I/O Kernel Int_Rom_Low 13 0a 0000-7fff 0 I/O Kernel Ext_Rom_Low 14 01 0000-3fff 0 Char Kernel Basic 15 00 0000-3fff 0 I/O Kernel Basic VDC $D600 This register map is from C-Hacking Magazine. ---------------------------------- | VDC 8563 Register Definitions | ---------------------------------- Reg 7 6 5 4 3 2 1 0 Description Notes ------ ---- ---- ---- ---- ---- ---- ---- ---- ------------------------ ----- 0 HzT7 HzT6 HzT5 HzT4 HzT3 HzT2 HzT1 HzT0 Horizontal Total ^1 1 HzD7 HzD6 HzD5 HzD4 HzD3 HzD2 HzD1 HzD0 Horizontal Displayed ^1 2 HzS7 HzS6 HzS5 HzS4 HzS3 HzS2 HzS2 HzS0 Horizontal Sync Position ^1 3 VSW3 VSW2 VSW1 VSW0 HSW3 HSW2 HSW1 HSW0 Vert/Horiz. Sync Width ^2 4 VeT7 VeT6 VeT5 VeT4 VeT3 VeT2 VeT1 VeT0 Vertical Total ^3 5 ....
Amiga7878