Digital Systems - Chapter07.pdf - po ang - Januszek66

CHAPTER 7

COUNTERS AND

REGISTERS

■

OUTLINE

Part 1

7-13

Wiring HDL Modules

Together

7-1

Asynchronous (Ripple)

Counters

7-14

State Machines

Part 2

7-2

Propagation Delay in

Ripple Counters

7-15

Integrated Circuit Registers

7-3

Synchronous (Parallel)

Counters

7-16

Parallel In/Parallel Out—

The 74ALS174/74HC174

7-4

Counters with MOD

Numbers

7-17

Serial In/Serial Out—

The 74ALS166/74HC166

6 2 N

7-5

Synchronous Down and

Up/ Down Counters

7-18

Parallel In/Serial Out—

The 74ALS165/74HC165

7-6

Presettable Counters

7-19

Serial In/Parallel Out—

The 74ALS164/74HC164

7-7

IC Synchronous Counters

7-8

Decoding a Counter

7-20

Shift-Register Counters

7-9

Analyzing Synchronous

Counters

7-21

Troubleshooting

7-22

HDL Registers

7-10

Synchronous Counter

Design

7-23

HDL Ring Counters

7-24

HDL One-Shots

7-11

Basic Counters Using HDLs

7-12

Full-Featured Counters

in HDL

■ OBJECTIVES

Upon completion of this chapter, you will be able to:

■

Understand the operation and characteristics of synchronous and

asynchronous counters.

Construct counters with MOD numbers less than 2 N .

■

Construct both up and down counters.

■

Connect multistage counters.

■

Analyze and evaluate various types of counters.

■

Design arbitrary-sequence synchronous counters.

■

Understand several types of schemes used to decode different types of

counters.

■

Describe counter circuits using different levels of abstraction in HDL.

■

Compare the major differences between ring and Johnson counters.

■

Recognize and understand the operation of various types of IC

registers.

■

Describe shift registers and shift register counters using HDL.

■

Apply existing troubleshooting techniques used for combinational logic

systems to troubleshoot sequential logic systems.

■

■ INTRODUCTION

In Chapter 5, we saw how flip-flops could be connected to function as coun-

ters and registers. At that time we studied only the basic counter and regis-

ter circuits. Digital systems employ many variations of these basic circuits,

mostly in integrated-circuit form. In this chapter, we will look at how FFs

and logic gates can be combined to produce different types of counters and

registers.

Because there are a great number of topics in this chapter, it has been

divided into two parts. In PART 1 , we will cover the principles of counter

operation, the various counter circuit arrangements, and representative IC

counters. PART 2 will present several types of IC registers, shift register

counters, and troubleshooting. Each part includes a section containing

HDL descriptions of counters and registers.

As you progress through this chapter, you will find that you are con-

stantly drawing on your understanding of the material we have covered in

the preceding chapters. It is a good idea to go back and review previously

learned material whenever you need to.

361

362

C HAPTER 7/ C OUNTERS AND R EGISTERS

PART 1

7-1

ASYNCHRONOUS (RIPPLE) COUNTERS

Figure 7-1 shows a four-bit binary counter circuit such as the one discussed

in Chapter 5. Recall the following points concerning its operation:

1. The clock pulses are applied only to the CLK input of flip-flop A . Thus, flip-

flop A will toggle (change to its opposite state) each time the clock pulses

make a negative (HIGH-to-LOW) transition. Note that J

1 for all FFs.

2. The normal output of flip-flop A acts as the CLK input for flip-flop B , and

so flip-flop B will toggle each time the A output goes from 1 to 0.

Similarly, flip-flop C will toggle when B goes from 1 to 0, and flip-flop D

will toggle when C goes from 1 to 0.

3. FF outputs D , C , B , and A represent a four-bit binary number, with D as

the MSB. Let’s assume that all FFs have been cleared to the 0 state

(CLEAR inputs are not shown). The waveforms in Figure 7-1 show that a

binary counting sequence from 0000 to 1111 is followed as clock pulses

are continuously applied.

4. After the NGT of the fifteenth clock pulse has occurred, the counter FFs

are in the 1111 condition. On the sixteenth NGT, flip-flop A goes from 1

to 0, which causes flip-flop B to go from 1 to 0, and so on, until the

CLK

*All J and K inputs

assumed to be 1.

123456789 0 1 2 3 4 5 6 7 8

CLOCK

DCBA

(count)

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000

0001

0010

Recycle to 0000

FIGURE 7-1

Four-bit asynchronous (ripple) counter.

363

S ECTION 7-1/ A SYNCHRONOUS (R IPPLE ) C OUNTERS

counter is in the 0000 state. In other words, the counter has gone through

one complete cycle (0000 through 1111) and has recycled back to 0000.

From this point, it will begin a new counting cycle as subsequent clock

pulses are applied.

In this counter, each FF output drives the CLK input of the next FF. This

type of counter arrangement is called an asynchronous counter because the

FFs do not change states in exact synchronism with the applied clock pulses;

only flip-flop A responds to the clock pulses. FF B must wait for FF A to

change states before it can toggle; FF C must wait for FF B , and so on. Thus,

there is a delay between the responses of successive FFs. This delay is

typically 5–20 ns per FF. In some cases, as we shall see, this delay can be

troublesome. This type of counter is also often referred to as a ripple counter

because of the way the FFs respond one after another in a kind of rippling

effect. We will use the terms asynchronous counter and ripple counter inter-

changeably.

Signal Flow

It is conventional in circuit schematics to draw the circuits (wherever possi-

ble) so that the signal flow is from left to right, with inputs on the left and

outputs on the right. In this chapter, we will often break with this conven-

tion, especially in diagrams showing counters. For example, in Figure 7-1, the

CLK inputs of each FF are on the right, the outputs are on the left, and the

input clock signal is shown coming in from the right. We will use this arrange-

ment because it makes the counter operation easier to understand and

follow (because the order of the FFs is the same as the order of the bits in the

binary number that the counter represents). In other words, FF A (which is

the LSB) is the rightmost FF, and FF D (which is the MSB) is the leftmost FF.

If we adhered to the conventional left-to-right signal flow, we would have to

put FF A on the left and FF D on the right, which is opposite to their posi-

tions in the binary number that the counter represents. In some of the

counter diagrams later in the chapter, we will employ the conventional left-

to-right signal flow so that you will get used to seeing it.

EXAMPLE 7-1

The counter in Figure 7-1 starts off in the 0000 state, and then clock pulses

are applied. Some time later the clock pulses are removed, and the counter

FFs read 0011. How many clock pulses have occurred?

Solution

The apparent answer seems to be 3 because 0011 is the binary equivalent of

3. With the information given, however there is no way to tell whether or not

the counter has recycled. This means that there could have been 19 clock

pulses; the first 16 pulses bring the counter back to 0000, and the last 3 bring

it to 0011. There could have been 35 pulses (two complete cycles and then

three more), or 51 pulses, and so on.

MOD Number

The counter in Figure 7-1 has 16 distinctly different states (0000 through

1111). Thus, it is a MOD-16 ripple counter. Recall that the MOD number is

generally equal to the number of states that the counter goes through in

364

C HAPTER 7/ C OUNTERS AND R EGISTERS

each complete cycle before it recycles back to its starting state. The MOD

number can be increased simply by adding more FFs to the counter. That is,

2 N

MOD number

(7-1)

where N is the number of FFs connected in the arrangement of Figure 7-1.

EXAMPLE 7-2

A counter is needed that will count the number of items passing on a con-

veyor belt. A photocell and light source combination is used to generate a

single pulse each time an item crosses its path. The counter must be able to

count as many as one thousand items. How many FFs are required?

Solution

It is a simple matter to determine what value of N is needed so that

Since 2 9

2 N

512, 9 FFs will not be enough. 2 10

1024, so 10 FFs

would produce a counter that could count as high as 1111111111 2

1000.

1023 10 .

Therefore, we should use 10 FFs. We could use more than 10, but it would be

a waste of FFs because any FF past the tenth one will not be needed.

Frequency Division

In Chapter 5, we saw that in the basic counter each FF provides an output

waveform that is exactly half the frequency of the waveform at its CLK input.

To illustrate, suppose that the clock signal in Figure 7-1 is 16 kHz. Figure 7-2

shows the FF output waveforms. The waveform at output A is an 8-kHz square

wave, at output B it is 4 kHz, at output C it is 2 kHz, and at output D it is

1 kHz. Notice that the output of flip-flop D has a frequency equal to the orig-

inal clock frequency divided by 16. In general,

In any counter, the signal at the output of the last FF (i.e., the

MSB) will have a frequency equal to the input clock frequency

divided by the MOD number of the counter.

For example, in a MOD-16 counter, the output from the last FF will have a

frequency of 1/16 of the input clock frequency. Thus, it can also be called a

divide-by-16 counter. Likewise, a MOD-8 counter has an output frequency of

the input frequency; it is a divide-by-8 counter.

CLOCK

FIGURE 7-2

Counter waveforms showing frequency division by 2 for each FF.

Digital Systems - Chapter07.pdf

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika: