pliki_krzepecki.doc

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--

-- Title       : wt

-- Design      : auto3

-- Author      : lab05

-- Company     : WTPW

--

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--

-- File        : wt.vhd

-- Generated   : Tue Jun  4 09:56:24 2013

-- From        : interface description file

-- By          : Itf2Vhdl ver. 1.20

--

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--

-- Description :

--

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--{{ Section below this comment is automatically maintained

--   and may be overwritten

--{entity {wt} architecture {wt}}

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity wt is

              port(

                            Ya : in STD_LOGIC;

                            Yb : in STD_LOGIC;

                            Yc : in STD_LOGIC;

                            L : in INTEGER range 0 to 8;

                            wyd : out INTEGER range 0 to 32

                   );

end wt;

--}} End of automatically maintained section

architecture wt of wt is

begin

              process (Ya, Yb, Yc, l)

              begin

              if Ya = '1' then

                            wyd <= 2 * L;

              elsif Yb = '1' then

                            wyd <= 3 * L;

              elsif Yc = '1' then

                            wyd <= 4 * L;

else

              wyd <= 0;

              end if;             

                            end process;

end wt;