74190.PDF

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M54/M74HC190
M54/M74HC191
4 BIT SYNCHRONOUS UP/DOWN COUNTERS
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HIGH SPEED
f
MAX
= 48 MHz (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 4
µA
(MAX.) AT T
A
= 25
°C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS190/191
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HCXXXF1R
M74HCXXXM1R
M74HCXXXB1R
M74HCXXXC1R
PIN CONNECTIONS
(top view)
DESCRIPTION
The M54/74HC190/191 are high speed CMOS 4-BIT
SYNCHRONOUS UP/DOWN COUNTERS fabri-
cated in silicon gate C
2
MOS technology.
They have the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.
State changes of the counter are synchronous with
the LOW-to-HIGH transition of the Clock Pulse input.
An asynchronous parallel load input overrides count-
ing and loads the data present on the DATA inputs into
the flip-flops, which makes it possible to use the cir-
cuits as programmable counters. A countenable input
serves as the carry/borrow input in multi-stage
counters. Control input, Down/Up, determines
whether a circuit counts up or down. A MAX/MIN out-
put and a Ripple Clock output provide overflow/under-
flow indication and make possible a variety of
methods for generating carry/borrow signals in multi-
stage counter applications.
All inputs are equipped with protection circuits against
static discharge and transient excess voltage.
October 1992
NC =
No Internal
Connection
1/14
M54/M74HC190/191
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
3, 2, 6, 7
4
5
11
12
13
14
15, 1, 10, 9
8
16
SYMBOL
QA to QD
ENABLE
U/D
LOAD
MA/MI OUT
RC
CLOCK
DA to DD
GND
V
CC
NAME AND FUNCTION
Flip-Flop Outputs
Count Enable Input
(Active LOW)
Parallel Data Input
Load Input (Active LOW)
Terminal Count Output
Ripple Clock Output
(Active LOW)
Cloack Input (LOW to
HIGH, Edge-triggered)
Data Inputs
Ground (0V)
Positive Supply Voltage
IEC LOGIC SYMBOL
(HC190)
IEC LOGIC SYMBOL
(HC191)
TRUTH TABLE
LOAD
L
H
H
H
H
INPUTS
ENABLE
D/U
X
L
L
H
X
X
L
H
X
X
CLOCK
X
QA
a
OUTPUS
QB
QC
b
c
UP COUNT
DOWN COUNT
NO CHANGE
NO CHANGE
QD
d
FUNCTION
PRESET DATA
UP COUNT
DOWN COUNT
NO COUNT
NO COUNT
X: Don’t Care
a - d: The level of steady state inputs at inputs a through D respectively
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M54/M74HC190/191
LOGIC DIAGRAM
(HC190)
3/14
M54/M74HC190/191
LOGIC DIAGRAM
(HC191)
4/14
M54/M74HC190/191
TIMING CHART
(HC190)
TIMING CHART
(HC191)
5/14

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