1256r1_1.pdf

(89 KB) Pobierz
MOTOROLA
SEMICONDUCTOR APPLICATION NOTE
Order this document
by AN1256/D
REV. 1.1
AN1256
Interfacing the HC05 MCU
to a Multichannel Digital-to-Analog Converter Using
the MC68HC705C8A and the MC68HC705J1A
By Mark Glenewinkel
CSIC Applications
Austin, Texas
INTRODUCTION
This application note describes the interface between Motorola's HC05 Family of microcontrollers and
Maxim’s MAX528/MAX529 (529) digital-to-analog converter (DAC). The 529 is an 8-bit, 8-channel, serial
interface DAC with programmable output buffers. The microcontroller unit (MCU) interface must be able to
"talk" to the 529 using a serial communication link. The serial peripheral interface (SPI) is one of the most
widely used serial transmission methods for communication between an MCU and a peripheral. This
application note describes the hardware and software design needed to link the SPI module on the
MC68HC705C8A MCU to the 529.
Not all HC05 Family members have SPI modules. An HC05 MCU without an SPI must interface with the
529 using a software input/output (I/O) driver. This method uses software bit programming to communicate
with the 529. Although not as efficient as the hardware SPI method, it provides MCUs with a means to
send data to the 529. This application note utilizes the MC68HC705J1A MCU to demonstrate the software
driver routine.
MAX529 DIGITAL-TO-ANALOG CONVERTER
Overview
The MAX529 is a monolithic device consisting of eight voltage output DACs. Two reference voltage inputs
feed two sets of four DACs on the chip. A serial interface is used to communicate with the chip. The
MAX528 operates from split supplies totaling up to 20 V, including +5 V and -15 V, +12 V and -5 V, and +15
V and -5 V, or a single supply up to 15 V. The MAX529 operates from 5 V supplies or from a single +5 V
supply. This application note utilizes the MAX529 with a single +5 V supply. If low-power consumption is
required, the part can be put in shutdown mode with its shutdown pin. During shutdown, the part uses less
than 50 A of current.
The part can configure its buffer mode of the DAC output pins in three different ways:
1) An unbuffered mode connects the internal R-2R DAC network directly to the output pin.
2) A full-buffered mode inserts an op amp buffer between the R-2R network and the output pin,
providing a +5 mA and -2 mA output drive.
3) A half-buffered mode is similar to the full-buffered mode but only provides up to +5 mA of output
drive in a unipolar configuration.
If needed, the part can be serially daisy-chained to other 529s to increase the number of DACs in a
system.
© Motorola, Inc., 1995
AN1256/D REV. 1.1
The R-2R DAC Network
The DAC inside the MAX529 is based on the R-2R resistor network. Most CMOS DACs are based on the
R-2R current steering circuit. Figure 1 shows a simple 2-bit R-2R DAC. A reference voltage is applied to
the V
REF
pin and the current, I, is binarily divided throughout the array as shown. These currents are
steered in discrete incremental amounts to the OUT1 and OUT2 nodes. The digital input to the DAC
determines the position of the switches used to steer the current. A logic one causes the switch to steer the
current to OUT1, while a logic zero causes the switch to steer the current to OUT2. OUT2 is at analog
ground. The feedback configuration of the op amp forces OUT1 to be at virtual ground potential.
V
REF
I
2R
1
0
R
I/4
2R
A
GND
I/2
2R
1
0
I/4
R
FB
OUT1
OUT2
A
GND
MSB
LSB
+
-
V
OUT
ANALOG OUTPUT
Figure 1. Simple 2-Bit Digital-to-Analog Converter
In this example, a digital value of 10
2
causes I/2 to flow to OUT1 and the remainder of the current flows to
OUT2. Therefore, 10
2
refers to half scale. If the input to the DAC was 11
2
, the output current would be full
scale minus one LSB. In this example, the full-scale current reading would be 3/4I.
The R-2R DAC will perform only if the OUT1 and OUT2 nodes are at the same potential. Therefore, a
current-to-voltage op amp converter is used. The feedback resistor R
FB
is made equal to R. The maximum
output voltage for this configuration is -I(1-2
-n
)R where n is the number of bits of DAC resolution. The minus
sign in the output voltage is a result of the current-to-voltage conversion. Another inverting op amp buffer
with gain of -1 may be used to create a positive output voltage. The resultant voltage output of the DAC
then can be defined as follows:
V
OUT
= V
REF
* (xx/2
n
)
where:
xx is the digital input to the DAC and n is the bit resolution of the DAC
For the 2-bit DAC above, the available output voltages are 0 V
REF
, 1/4 V
REF
, 1/2 V
REF
, and 3/4 V
REF
.
Inside the MAX529
As stated earlier, the 529 contains eight latched 8-bit DACs, eight buffer amplifiers, serial control logic, and
two reference inputs. The buffer amplifiers can be configured as buffered, half buffered, and unbuffered.
With one 16-bit serial transmission, any or all of the eight voltage outputs can be programmed. Figure 2
shows the block diagram of the 529.
MOTOROLA
2
AN1256/D
The 529 DACs are divided into two groups of four DACs. Each group has its own REFH and REFL analog
input reference voltages. The output of a DAC is defined as
V
OUT
= (REFH-REFL) * (xx/256 + REFL)
where:
xx is the 8-bit digital input code with a range of 0-255.
Unbuffered mode connects the internal R-2R DAC network directly to the output pin. Full-buffered and
half-buffered modes allow the user to drive more of a load directly on the outputs of the 529. All electrical
specs for operating voltages, reference voltages, and buffer modes can be found in greater detail in the
529 data sheet.
Digital Interface
The digital interface to the 529 is composed of a serial data port that synchronously transmits 16-bit data.
It also is capable of being shut down by an external pin to conserve power.
CS
Active-Low Chip Select
When asserted low, this input pin initializes the 529 to start a new frame of serial data. When
asserted high, the 16-bit data is latched and the internal shift register is turned off. The DAC
registers also are updated with the new data.
DOUT Serial Data Out
This open drain pin serves as the serial output data from the DIN pin.
DIN
Serial Data In
This pin serves as the input data line that receives the 16-bit serial data stream.
Serial Data Clock
This pin is an input that drives the serial transmission lines.
CLK
SHDN Shutdown
Connect this input pin high for normal operation. Connect it low to conserve power.
Serial data is clocked in at DIN on the rising edge of CLK after CS is asserted low. Refer to Figure 3. After
all 16 bits have been clocked in, the CS pin is negated to latch the data. The DAC outputs and buffers will
be changed according to the latched data. The serial output DOUT pin is an open-drain FET that requires
a pullup resistor (typically 4.7 KΩ ) to V . Any number of 529s can be daisy-chained together by
DD
connecting the DOUT pin of one device to the DIN pin of the following device in the chain.
DAC Programming
The 529 is programmed with 16 bits of information. The first eight bits contain the address pointer and the
second eight bits contain the data byte. These bits enter a shift register serially through DIN with A7 first
and D0 last.
Setting the DAC Outputs
To program one of the eight DACs, the corresponding bit in the address pointer must be set and the data
byte must hold the digital data to set the correct voltage for that output. Any or all of the outputs may be set
according to the address pointer. This instruction will change only the outputs, not the buffers.
AN1256/D
MOTOROLA
3
Setting the Buffers
To set the buffers, all address pointer bits must be set to zero and data bit D7 is one. When this instruction
is sent to the 529, data bit D6 is ignored and D5-D0 is latched into the mode registers only. The DAC
registers are unaffected. Refer to Table 1 for programming the buffers.
Table 1. Buffer Mode Programming
Mode
Unbuffered
(D0 = D3 = X)
Half-Buffered
D3 = 0
D5 = 1
Full-Buffered
D3 = 1
D0 = 1
D4 = 1
D2 = 1
D0 = 0
D1 = 1
OUT0,1
D5 = 0
D5 = 1
OUT2,3
D4 = 0
D4 = 1
OUT4,5
D2 = 0
D2 = 1
OUT6,7
D1 = 0
D1 = 1
Programming for Multiple 529s
When programming other 529s configured in a daisy-chain arrangement, use the no operation instruction
(NOP) as a place setter. NOP is implemented when all address pointer bits and all data bits are set to zero.
When latched into the 529, all outputs and buffers are unaffected.
MOTOROLA
4
AN1256/D
REFH1 REFL1
LATCH
8-BIT DAC
OUT0
LATCH
8-BIT DAC
OUT1
LATCH
8-BIT DAC
OUT2
DIN
DOUT
CLK
CS
SHDN
CONTROL
LOGIC
LATCH
8-BIT DAC
OUT3
LATCH
8-BIT DAC
OUT4
LATCH
8-BIT DAC
OUT5
LATCH
8-BIT DAC
OUT6
LATCH
8-BIT DAC
OUT7
REFH2 REFL2
Figure 2. MAX528/529 Block Diagram
CS
CLK
DIN
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Current Instruction
DOUT
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Previous Instruction
Figure 3. MAX529 Timing Diagram
AN1256/D
MOTOROLA
5

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin