compal_la-5251p_r0.9_schematics.pdf
(
1356 KB
)
Pobierz
A
B
C
D
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1
1
Compal Confidential
Schematics Document
2
2
INTEL Auburndale BGA with IBEX core logic
Swatch UMA
LA-5251P
3
3
2010-01-04
REV:0.9
4
4
Compal Electronics, Inc.
Security Classification
Compal Secret Data
2008/09/15
2010/12/31
Title
Issued Date
Deciphered Date
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
R ev
Custom
LA-5251P
0.9
Date:
Tuesday, January 05, 2010
Sheet
1
o f
47
A
B
C
D
E
A
B
C
D
E
Swatch UMA
Compal Confidential
XDP Conn.
Accelerometer
File Name : LA-5251P
Page 4
LIS302DLTR
Mobile
Page 24
Display port panel
Page 20
PEG-eDP
1
1
Fan Control
Auburndale CPU
DDR3 1066/1333MHz 1.5V
DDR3-SO-DIMM X 2
Page 4
BANK 0, 1, 2, 3
Page 9,10
BGA 1288pins
Dual Channel
Thermal Sensor
EMC2113
RGB
Page 4,5,6,7,8
VGA
Page 18
Page 4
DP *1(Docking)
Page 29
FDI
DMI X4
Display port
Page 18
DDI_D
CK505
Clock Generator
SL G8SP585VTR
USB *1(Docking)
Page 29
DDI_B
USB conn*1(Left side)
Page 11
DDI
Page 24
Express Card 54
PCIE *1 + USB *1
WWAN
+SIM Card
2
USB2.0
2
FingerPrinter Validity VFS451
USB*1
USB2.0
Intel Ibex Peak M
daughter board Module
Page 32
USB*1
Page 23
Page 23
Azalia
USB conn x 3(For I/O)-Rear side, Power USB
10 71pins
25mm*27mm
PCI-E BUS
BT Conn USB x 1
SATA0
SATA1
Page 24
USB x1(Camara)
Controller
10/100/1000 LAN
Intel Hanksville GbE
WLAN Card
Rico R5C835
Page 20
PCI BUS
SATA3
Page 12,13,14,15,16,17
Page 25
MDC V1.5
PHY
PCIE*1
R J11
Page 21
Page 22
ONFI Interface
Page 28
Page 28
TPA6047A4RHBR
Audio CKT
Braidwood
AMP & Audio Jack
IDT 92HD75
Page 27
RJ45 CONN
Page 23
Page 26
1394 port
Smart Card
SD/MMC Slot
3
Page 21
3
Page 25
Page 25
Page 32
SATA ODD Connector
Page 22
NAND Flash Card
Page 23
1.8" SATA HDD Connector
LPC BUS
Page 22
RTC CKT.
L ED
Docking CONN.
(2) USB 1.channels
(1) Display Port Channels
(1) Line
Page 29
Page 12
LED Board
Page 28
TPM1.2
SATA*1(Docking)
SMSC KBC 1098
In
Power OK CKT.
Page 29
SLB9635TT
(1) Line
Out
(1) RJ45 (10/100/1000)
(1) V
Page 33
page 30
Page 32
GA
(1) 2 LAN indicator LED's
(1) Power Button
(1) SATA
Touch Pad CONN.
4
Int.KBD
4
Power On/Off CKT.
Page 28
Page 28
Page 28
TrackPoint CONN.
Page 28
Compal Electronics, Inc.
Security Classification
Compal Secret Data
DC/DC Interface CKT.
2008/09/15
2010/12/31
Title
Issued Date
Deciphered Date
8 MB
Block Diagram
SPI ROM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Page 34
Page 31
Size
Document Number
R ev
Custom
LA-5251P
0.9
Date:
Tuesday, January 05, 2010
Sheet
2
o f
47
A
B
C
D
E
A
( O MEANS ON
X MEANS OFF )
Voltage Rails
Symbol Note :
+RTCVCC
+B
+5VALW
+3VM
+1.05VM
+1.5V
+5VS
+3VL
+3VALW
+0.75V
+3VS
: means Digital Ground
+1.5VS
power
plane
+VCCP
+CPU_CORE
: means Analog Ground
+1.05VS
+1.8VS
@ : means just reserve , no build
CONN@ : means ME part.
State
SV@ : means just build on SV Sku. LV Sku no build.
LV@ : means just build on LV Sku. SV Sku no build.
L
Layout Notes
01/04 update
S0
O
O
O
O
O
O
: Question Area Mark.(Wait check)
S1
O
O
O
O
O
O
S3
O
O
O
O
O
X
Install below 45 level BOM structure for ver. 0.1
O
O
S5 S4/AC
O
O
X
X
45@ : means just put it in the BOM of 45 level.
S5 S4/ Battery only
O
O
X
X
X
X
S5 S4/AC & Battery
don't exist
O
X
X
X
X
X
Install below 43 level BOM structure for ver. 0.1
1
1
DEBUG@ : means just build when PCIE port 80 CARD function enable.
Remove before MP
SMBUS Control Table
THERMAL
SOURCE
BATT
XDP
SODIMM
CLK CHIP
MINI CARD
DOCK
NIC
SENSOR
G-SENSOR
X
X
X
X
X
X
X
X
X
X
V
SMB_EC_CK1
SMB_EC_DA1
SMSC1098
X
X
V V
V
V
V
V
SMBCLK
Calpella
SMBDATA
X
X
X X
X
X
X
X
X
X
V
SML0CLK
SML0DATA
Calpella
X
X
X
X
V
V
SML1CLK
SML1DATA
Calpella
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/09/15
2010/12/31
Title
Issued Date
Deciphered Date
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
Document Number
R ev
Custom
0.9
LA-5251P
Date:
Tuesday, January 05, 2010
Sheet
3
o f
47
A
1
2
3
4
5
Layout rule 10mil width
trace
length < 0.5", spacing 20mil
U 1B
20_0402_1%
R2
H_COM P3
H_COM P2
H_COM P1
H_COM P0
1
2
AD71
COMP3
C LK_CPU_BCLK
AK7
CLK_CPU_BCLK
15
BCLK
20_0402_1%
R5
CLK_CPU_BCLK#
1
2
AC70
AK8
COMP2
BCLK#
CLK_CPU_BCLK#
15
49.9_0402_1%
1
R7
2
AD69
K71
CLK_CPU_XDP
COMP1
BCLK_ITP
J70
CLK_CPU_XDP#
BCLK_ITP#
49.9_0402_1%
R9
07/09 update for INTEL S3 leakage issue.
1
2
AE66
COMP0
CLK_EXP
L21
CLK_EXP
13
PEG_CLK
C LK_EXP#
J21
PEG_CLK#
CLK_EXP#
13
+1.5V
TP_SKTOCC#
M71
P AD
T48
PROC_DETECT
R 1093
Y2
DPLL_REF_SSCLK
C LK_DP
13
A
A
W4
2
1
DPLL_REF_SSCLK#
CLK_DP#
13
H _CATERR#
N61
CATERR#
1K_0402_5%
SM_D RAMRST#
1
6
DRAMRST#
9,10
BJ12
SM_D RAMRST#
SM_DRAMRST#
1
R 14
2
H_PECI_ISO
N19
Q52A
2N7002DWH 2N SOT363-6
15
H _ PECI
PECI
0_0201_5%
BV33
SM_RCOMP0
2
R 1092
100K_0402_5%
1
SM_RCOMP[0]
SM_RCOMP1
BP39
SM_RCOMP[1]
P C H _ DDR_RST
15
to power; PU to VCCP at power side also
SM_RCOMP2
@
BV40
SM_RCOMP[2]
1
R 15
2
H _ PROCHOT#_D
N67
C6
1
2
.1U_0402_16V7K
40
H _PROCHOT#
PROCHOT#
0_0201_5%
AV66
PM_EXTTS#0
T49
P AD
PM_EXT_TS#[0]
AV64
PM_EXTTS#1
1
2
PM_EXT_TS#[1]
PM_EXTTS#1_R
9 ,10
0_0201_5%
R 16
from DDR
07/17 update
08/28 update
R 17
H_THERMTRIP#_R
1
2
N17
15
H_THERMTRIP#
THERMTRIP#
0_0201_5%
U71
XDP_PRDY#
PRDY#
U69
XDP _PREQ#
PREQ#
H _CPURST#
R 18
H _ CPURST#_R
H _P M_SYNC_R
X DP_TCK
1
2
N70
T67
RESET_OBS#
TCK
0_0201_5%
N65
XDP_TMS
TMS
1
R 19
2
M17
P69
XDP_TRST#
14
H _ PM_SYNC
PM_SYNC
TRST#
0_0201_5%
XD P_TDI
CPU XDP Connector
T69
TDI
X DP_TDO
T71
TDO
X DP_TDI_M
P71
TDI_M
H _C P U P W RGD
1
R 21
2
SYS_AGENT_P WROK
AM7
T70
XDP _PREQ#
JP4
VCCPWRGOOD_1
TDO_M
0_0201_5%
XDP_PRDY#
1
2
GND0
GND1
W71
XDP _DBRESET#
3
4
DBR#
OBSFN_A0
OBSFN_C0
C F G 8
5
R 22
V C C PWRGOOD_0
XDP_BPM#0
R 23
0_0201_5%
1
2
Y67
1
2
5
6
15
H _C P U P W RGD
VCCPWRGOOD_0
OBSFN_A1
OBSFN_C1
C F G 9
5
0_0201_5%
@
R 24
0_0201_5%
1
2
7
8
5
C F G 12
GND2
GND3
XDP_BPM#0
XDP_BPM#1
J69
R 25
1
2
0_0201_5%
9
10
BPM#[0]
OBSDATA_A0
OBSDATA_C0
C F G 0
5
B
B
1
R 26
2
V D D P W RGOOD_R
AM5
J67
XDP_BPM#1
@
R 27
1
2
0_0201_5%
11
12
14
PM_DRAM_PWRGD
SM_DRAMPWROK
BPM#[1]
5
C F G 13
OBSDATA_A1
OBSDATA_C1
C F G 1
5
0_0201_5%
J62
XDP_BPM#2
XDP_BPM#2
R 28
1
2
0_0201_5%
13
14
BPM#[2]
GND4
GND5
from power
K65
XDP_BPM#3
@
R 29
1
2
0_0201_5%
15
16
BPM#[3]
5
C F G 14
OBSDATA_A2
OBSDATA_C2
C F G 2
5
XDP_BPM#4
XDP_BPM#6
XDP_BPM#3
R 30
0_0201_5%
H15
K62
1
2
17
18
32
VTTPWRGOOD
VTTPWRGOOD
BPM#[4]
OBSDATA_A3
OBSDATA_C3
C F G 3
5
XDP_BPM#5
@
R 31
0_0201_5%
J64
1
2
19
20
5
C F G 15
BPM#[5]
GND6
GND7
0_0201_5%
+3VS
K69
21
22
BPM#[6]
5
C F G17
OBSFN_B0
OBSFN_D0
C F G 10
5
H_PWRGD_XDP
1
R 32
2
H _PWRGD_XDP_R
Y70
M69
XDP_BPM#7
ESD request to add
23
24
TAPPWRGOOD
BPM#[7]
5
C F G16
OBSFN_B1
OBSFN_D1
C F G 11
5
25
26
GND8
GND9
R 33
PLT_RST#_R
XDP_BPM#4
0_0201_5%
R 43
XD P_BPM#4_R
1
2
G3
1
2
27
28
15
BUF_PLT_RST#
RSTIN#
OBSDATA_B0
OBSDATA_D0
C F G 4
5
XDP_BPM#5
0_0201_5%
R 48
XD P_BPM#5_R
1
2
29
30
OBSDATA_B1
OBSDATA_D1
C F G 5
5
1.5K_0402_1%
R 34
1K_0201_5%
31
32
GND10
GND11
+VCCP
XDP_BPM#6
XDP_BPM#7
0_0201_5%
1
2
R 40
XD P_BPM#6_R
33
34
OBSDATA_B2
OBSDATA_D2
C F G 6
5
0_0201_5%
1
2
R 41
XD P_BPM#7_R
35
36
OBSDATA_B3
OBSDATA_D3
C F G 7
5
R 35
750_0402_1%
INTEL_AUBURNDALE_1288
R 36
1K_0201_5%
1
37
38
1
GND12
GND13
H _C P U P W RGD
H _C P U P W RGD_R
CLK_CPU_XDP
2
39
40
PWRGOOD/HOOK0
ITPCLK/HOOK4
+ VCCP
C1
0.1U_0402_16V4Z
@
PM_PWRBT N#_R
CLK_CPU_XDP#
41
42
14
PM_PWRBTN#_R
HOOK1
ITPCLK#/HOOK5
1K_0201_5%
43
44
2
VCC_OBS_AB
VCC_OBS_CD
H_PWRGD_XDP
1
2
45
46
XDP_RST#_R
R 38
1
2
H _CPURST#
HOOK2
RESET#/HOOK6
R 37
0_0201_5%
47
48
XDP_DB RESET#_R
1
2
XDP _DBRESET#
HOOK3
DBR#/HOOK7
XDP_DBRESET#
12,14
49
50
R 39
0_0201_5%
GND14
GND15
0112 Add test points
X DP_TDO
51
52
P AD
T112
SDA
TD0
XDP_TRST#
53
54
P AD
T113
SCL
TRST#
55
56
XD P_TDI
TCK1
TDI
X DP_TCK
57
58
XDP_TMS
TCK0
TMS
PM_PWRBT N#_R
59
60
GND16
GND17
1
1
C 120
0.1U_0402_16V4Z
C 1 19
0.1U_0402_16V4Z
SAMTE_BSH-030-01-L-D-A
C O N N @
01/04 update for ESD
XDP_RST#_R
@
P LT_RST#
1
2
PLT_RST#
12,15,21,22,23,31
07/08 update for INTEL S3 leakage issue.
07/17 update for value change back
R 42
0_0201_5%
2
2
PM_PWRBT N#_R
V D D P W RGOOD_R
1
2
1
2
+VCCP
V CCP_1.5VSPWRGD
32
C
@
1K_0201_5%
R 20
R 12
1.5K_0402_1%
L
C
Add C119 between JP4 pin 37 and 41;
Add C120 close to R20.1
1
2
R 13
750_0402_1%
Thermal Sensor EMC2113 with CPU PWM FAN
F AN_PWM_R
1
2
FAN_PWM
30
+3VS
R 46
0_0201_5%
11/06 update
2
Processor Pullups
C2
0.1U_0402_16V4Z
DDR3 Compensation Signals
DDR Pullups
L
Close to U2
@
U2
2
1
R 50
68_0402_5%
C5
2200P_0402_50V7K
SM_RCOMP0
SM_RCOMP1
+VCCP
H _ THERMDC
H_THERM DA
REMOTE2+
REMOTE2-
+5VS
1
2
1
16
DN
DP2/DN3
R 52
100_0201_1%
1
+ VCCP
1
2
H _CATERR#
H _ PROCHOT#_D
H _ CPURST#_R
R 44
1
2
49.9_0402_1%
1
2
2
15
DP
DN2/DP3
R 56
24.9_0402_1%
C3
2200P_0402_50V7K
2.05K_0402_1%
SM_RCOMP2
PM_EXTTS#0
+3VS _THER
R 51
1
2
1
2
1
2
3
14
VDD
TRIP_SET
R 58
130_0402_1%
R 45
68_0402_5%
R1
10K_0201_5%
R 54
10K_0201_5%
15K_0402_5%
PM_EXTTS#1
C4
0.1U_0402_16V4Z
F AN_PWM_R
R 55
1
2
1
2
1
4
13
+3VS
PWM_IN
SHDN_SEL
R 47
@
68_0402_5%
R3
10K_0201_5%
J P2
Layout Note:Please these
resistors near Processor
1
2
5
12
+3VS
ADDR_SEL
GND
R 71
10K_0201_5%
1
1
2
FAN_PWM_OUT
6
11
2
15
THERM_SCI#
ALERT#
PWM
2
10K_0201_5%
R 61
3
+5VS
3
@
T ACH
1
2
7
10
4
+3VS
SYS_SHDN#
TACH
4
0112 Remove uninstall parts
R 62
10K_0201_5%
5
G5
8
9
6
9,10,11,13,24
SMB_DATA_S3
SMDATA
SMCLK
SMB_CLK_S3
9,10,11,13,24
G6
EMC2113-1-AP-TR QFN 16P
ACES_85205-04001
C O N N @
XDP_TRST#
11/06 Cancel REMOTE thermal sensor reserve.
1
2
R 59
51_0402_5%
H_THERMT RIP#
1
2
R 63
0_0201_5%
Add 0ohm and 0.1u
D
Close to XDP
D
+ VCCP
X DP_TDO
1
2
R 10
51_0402_5%
This shall place near XDP
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2008/09/15
2010/12/31
Title
Issued Date
Deciphered Date
Auburndale(1/5)-Thermal/XDP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
D ocument Number
R e v
C us tom
0.9
L A -5251P
D at e:
Tuesday, January 05, 2010
Sheet
4
o f
47
1
2
3
4
5
1
2
3
4
5
U 1A
49.9_0402_1%
1
E XP_ICOMPI
R 64
B12
2
PEG_ICOMPI
A13
PEG_ICOMPO
F7
D12
14
DMI_CRX_PTX_N0
DMI_RX#[0]
PEG_RCOMPO
J8
B11
E XP_RBIAS
1
R 65
750_0402_1%
2
U 1E
14
DMI_CRX_PTX_N1
DMI_RX#[1]
PEG_RBIAS
K8
14
DMI_CRX_PTX_N2
DMI_RX#[2]
J4
G40
W66
14
DMI_CRX_PTX_N3
T116 P AD
DMI_RX#[3]
PEG_RX#[0]
RSVD32
G38
W64
T117 P AD
PEG_RX#[1]
RSVD33
F9
H34
14
DMI_CRX_PTX_P0
DMI_RX[0]
PEG_RX#[2]
J6
P34
14
DMI_CRX_PTX_P1
DMI_RX[1]
PEG_RX#[3]
A
A
K9
G28
AC69
14
DMI_CRX_PTX_P2
DMI_RX[2]
PEG_RX#[4]
RSVD34
J2
H25
AC71
04/20 INTEL #418125 update
14
DMI_CRX_PTX_P3
DMI_RX[3]
PEG_RX#[5]
RSVD35
T118 P AD
H24
PEG_RX#[6]
H17
D29
AA71
T119 P AD
14
DMI_CTX_PRX_N0
DMI_TX#[0]
PEG_RX#[7]
RSVD36
K15
B26
AA69
14
DMI_CTX_PRX_N1
DMI_TX#[1]
PEG_RX#[8]
RSVD37
J13
D26
14
DMI_CTX_PRX_N2
DMI_TX#[2]
PEG_RX#[9]
F10
B23
C F G 0
AL4
R66
14
DMI_CTX_PRX_N3
DMI_TX#[3]
PEG_RX#[10]
4
C F G 0
CFG[0]
RSVD38
C F G 1
D22
AM2
R64
PEG_RX#[11]
4
C F G 1
CFG[1]
RSVD39
C 9 03
C F G 2
G17
A20
AK1
14
DMI_CTX_PRX_P0
DMI_TX[0]
PEG_RX#[12]
4
C F G 2
CFG[2]
M15
D19
MB_C_D P_AUXN
1
2
C F G 3
C F G 5
AK2
14
DMI_CTX_PRX_P1
DMI_TX[1]
PEG_RX#[13]
MB_DP_AUXN
20
4
C F G 3
CFG[3]
G13
A17
C F G 4
C F G 6
AK4
14
DMI_CTX_PRX_P2
DMI_TX[2]
PEG_RX#[14]
4
C F G 4
CFG[4]
J11
B14
0.1U_0402_16V4Z
AJ2
BT5
14
DMI_CTX_PRX_P3
DMI_TX[3]
PEG_RX#[15]
4
C F G 5
CFG[5]
RSVD_NCTF[3]
AT2
BR5
4
C F G 6
CFG[6]
RSVD_NCTF[4]
T120 P AD
C F G 7
F40
AG7
4
C F G 7
PEG_RX[0]
CFG[7]
C F G 8
J38
AF4
BV6
PEG_RX[1]
4
C F G 8
CFG[8]
RSVD_NCTF[2]
G34
C F G 9
AG2
BV8
PEG_RX[2]
4
C F G 9
CFG[9]
RSVD_NCTF[1]
+ VCCP
FDI_CT X_PRX_N0
FDI_CT X_PRX_N1
FDI_CT X_PRX_N2
FDI_CT X_PRX_N3
FDI_CT X_PRX_N4
FDI_CT X_PRX_N5
FDI_CT X_PRX_N6
FDI_CT X_PRX_N7
L2
M34
C F G10
AH1
14
FDI_CTX_PRX_N0
FDI_TX#[0]
PEG_RX[3]
4
C F G10
CFG[10]
N7
J28
C F G11
AC2
AV69
14
FDI_CTX_PRX_N1
FDI_TX#[1]
PEG_RX[4]
4
C F G11
CFG[11]
RSVD45
C F G12
M4
G25
AC4
AK71
14
FDI_CTX_PRX_N2
FDI_TX#[2]
PEG_RX[5]
4
C F G12
CFG[12]
RSVD46
C F G13
P1
K24
AE2
AN69
14
FDI_CTX_PRX_N3
4
C F G13
FDI_TX#[3]
PEG_RX[6]
CFG[13]
RSVD47
N10
B28
R 8 01
7.5K_0402_1%
C F G14
C F G15
C F G16
C F G17
AD1
AP66
14
FDI_CTX_PRX_N4
FDI_TX#[4]
PEG_RX[7]
4
C F G14
CFG[14]
RSVD48
R7
A27
AF8
AH66
14
FDI_CTX_PRX_N5
FDI_TX#[5]
PEG_RX[8]
4
C F G15
CFG[15]
RSVD49
U7
B25
AF6
AK66
14
FDI_CTX_PRX_N6
FDI_TX#[6]
PEG_RX[9]
4
C F G16
CFG[16]
RSVD50
W8
A24
AB7
AR71
14
FDI_CTX_PRX_N7
FDI_TX#[7]
PEG_RX[10]
4
C F G17
CFG[17]
RSVD51
B21
AM66
PEG_RX[11]
RSVD52
B19
AK69
PEG_RX[12]
RSVD53
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
K1
B18
MB_C _DP_AUXP
1
2
AU71
14
FDI_CTX_PRX_P0
FDI_TX[0]
PEG_RX[13]
MB_DP_AUXP
20
RSVD54
N5
B16
C 904
0.1U_0402_16V4Z
AT70
14
FDI_CTX_PRX_P1
FDI_TX[1]
PEG_RX[14]
RSVD55
N2
D15
AR69
14
FDI_CTX_PRX_P2
FDI_TX[2]
PEG_RX[15]
RSVD56
Q46A
R2
AU69
14
FDI_CTX_PRX_P3
FDI_TX[3]
RSVD57
N9
N40
AT67
14
FDI_CTX_PRX_P4
FDI_TX[4]
PEG_TX#[0]
RSVD58
R8
L38
2
14
FDI_CTX_PRX_P5
FDI_TX[5]
PEG_TX#[1]
MB_DP_HPD
20
B
B
U6
M32
AU1
AP2
P AD
T50
T51
P AD
14
FDI_CTX_PRX_P6
FDI_TX[6]
PEG_TX#[2]
RSVD_TP[0]
RSVD_TP[2]
W10
D40
2N7002DWH 2N SOT363-6
AN7
T52
P AD
14
FDI_CTX_PRX_P7
FDI_TX[7]
PEG_TX#[3]
RSVD_TP[1]
A38
R 8 00
100K_0402_5%~D
PEG_TX#[4]
F D I_F S Y N C0
AC7
G32
T4
AV4
14
F D I_F S Y N C 0
FDI_FSYNC[0]
PEG_TX#[5]
RSVD15
RSVD62
F D I_F S Y N C1
F D I _INT
AC9
B33
T2
AU2
14
F D I_F S Y N C 1
FDI_FSYNC[1]
PEG_TX#[6]
RSVD16
RSVD63
B35
PEG_TX#[7]
AB5
L30
U1
BE69
14
F D I_ INT
FDI_INT
PEG_TX#[8]
RSVD17
RSVD64
A31
V2
BE71
PEG_TX#[9]
RSVD18
RSVD65
F D I_LS Y NC0
AA1
B32
14
F D I_LS Y NC0
FDI_LSYNC[0]
PEG_TX#[10]
F D I_LS Y NC1
AB2
L28
AV71
14
F D I_LS Y NC1
FDI_LSYNC[1]
PEG_TX#[11]
RSVD19
N26
AW70
PEG_TX#[12]
RSVD20
M24
BV71
PEG_TX#[13]
DC_TEST_BV71
G21
C 9 05
AY69
BV69
PEG_TX#[14]
RSVD21
DC_TEST_BV69
J20
MB_C_DP_D ATA0_N
1
2
BB69
BV68
PEG_TX#[15]
MB_DP_DATA0_N
20
RSVD22
DC_TEST_BV68
BV5
DC_TEST_BV5
0.1U_0402_16V4Z
L40
D8
BV3
PEG_TX[0]
RSVD23
DC_TEST_BV3
N38
B7
BV1
PEG_TX[1]
RSVD24
DC_TEST_BV1
N32
BT71
PEG_TX[2]
DC_TEST_BT71
B39
A10
BT69
PEG_TX[3]
RSVD26
DC_TEST_BT69
B37
B9
BT3
PEG_TX[4]
RSVD27
DC_TEST_BT3
H32
BT1
PEG_TX[5]
DC_TEST_BT1
A34
C5
BR71
VSS_NCTF2_R
8
PEG_TX[6]
RSVD_NCTF[7]
DC_TEST_BR71
D36
A6
BR1
PEG_TX[7]
RSVD_NCTF[8]
DC_TEST_BR1
VSS_NCTF6_R
8
J30
E71
PEG_TX[8]
DC_TEST_E71
B30
E3
E1
PEG_TX[9]
RSVD_NCTF[6]
DC_TEST_E1
D33
F1
C71
PEG_TX[10]
RSVD_NCTF[5]
DC_TEST_C71
N28
C69
PEG_TX[11]
DC_TEST_C69
M25
C3
PEG_TX[12]
DC_TEST_C3
N24
A71
PEG_TX[13]
DC_TEST_A71
F21
C 8 58
A69
PEG_TX[14]
DC_TEST_A69
L20
MB_C_D P_DATA0_P
1
2
A68
PEG_TX[15]
MB_DP_DATA0_P
20
DC_TEST_A68
VSS_NCTF1_R
8
A5
DC_TEST_A5
VSS_NCTF7_R
8
C
0.1U_0402_16V4Z
C
INTEL_AUBURNDALE_1288
INTEL_AUBURNDALE_1288
CFG Straps for PROCESSOR
R 68
C F G 0
@
3.01K_0402_1%
1
2
PCI-Express Configuration Select
CFG0
1: Single PEG
0: Bifurcation enabled
Not applicable for Clarksfield Processor
C F G 3
R 69
1
2
@
3.01K_0402_1%
CFG3-PCI Express Static Lane Reversal
CFG3
1: Normal Operation
15 -> 0, 14 ->1, .....
0: Lane Numbers Reversed
C F G 4
R 70
1
2
3.01K_0402_1%
D
ES1 sample need negative voltage
ES2 sample contact to GND
D
CFG4-Display Port Presence
1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
Compal Electronics, Inc.
Compal Secret Data
Security Classification
device is connected to the Embedded
Display Port
2008/09/15
2010/12/31
Title
Issued Date
Deciphered Date
Auburndale(2/5)-DMI/PEG/FDI
C us tom
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
D ocument Number
R e v
0.9
L A -5251P
D at e:
Tuesday, January 05, 2010
Sheet
5
o f
47
1
2
3
4
5
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